// Copyright (C) 1953-2022 NUDT
// Verilog module name - cpu_report
// Version: V4.1.0.20221209
// Created:
//         by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module cpu_report 
#(
parameter local_module_id = 12'd0
)
(
    i_clk  ,
    i_rst_n,
	
	iv_hcp_mid                            ,
	iv_os_cid                             ,
	
	iv_port_ptp_enabled                   ,    
    iv_measure_sync_state_report_enabled  ,
    i_cyclestart                          ,
    
    iv_frequency_cor                      ,

    iv_gm_timestamps         ,
    iv_correctfield_time     ,
    iv_local_cnt_rx          ,
    iv_sync_correctfield_time,
    iv_sync_link_delay       ,
    i_time_info_valid        , 
    
    iv_clk_set               ,
    i_clk_set_wr             ,
    iv_current_local_count   ,
    iv_current_sync_clk      ,
    
	i_sync_ok                             ,
	iv_sync_abnormal_cnt                  ,
	iv_offset                             ,
	iv_csrateoffset_previousnode          ,
    i_csrateoffset_previousnode_wr        ,
	i_sync_state_wr                       ,
	
	iv_t1                                 ,
    iv_t2                                 ,
    iv_t3                                 ,	
    iv_t4                                 ,
	i_measure_state_wr                    ,
	
	ov_data                               ,
	o_data_wr                             
);

// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n; 

input      [11:0]       iv_hcp_mid;
input      [11:0]       iv_os_cid ;
// pkt input                       
input      [31:0]       iv_port_ptp_enabled     ;
input                   iv_measure_sync_state_report_enabled;
input                   i_cyclestart;

input      [48:0]       iv_frequency_cor       ;

input     [79:0]	    iv_gm_timestamps         ;
input     [63:0]	    iv_correctfield_time     ;
input     [39:0]	    iv_local_cnt_rx          ;
input     [63:0]        iv_sync_correctfield_time;
input     [27:0]        iv_sync_link_delay       ;
input      	            i_time_info_valid        ; 

input     [95:0]	    iv_clk_set             ;
input    	            i_clk_set_wr           ;
input     [39:0]        iv_current_local_count ;
input     [95:0]        iv_current_sync_clk    ;

input                   i_sync_ok                         ;
input	   [15:0]	    iv_sync_abnormal_cnt              ;
input	   [12:0]       iv_offset                         ;
input	   [31:0]    	iv_csrateoffset_previousnode      ;
input                   i_csrateoffset_previousnode_wr    ;
input                   i_sync_state_wr                   ;
// pkt output to NMA
input      [95:0]       iv_t1                             ;
input      [95:0]       iv_t2                             ;
input      [95:0]       iv_t3                             ;
input      [95:0]       iv_t4                             ;
input                   i_measure_state_wr                ;

output     [8:0]        ov_data               ;
output                  o_data_wr             ; 

wire       [4:0]	    wv_fifo_data_count_fifo2ctx        ;
wire      	            w_fifo_rden_ctx2fifo               ;
wire       [319:0]      wv_fifo_rdata_fifo2ctx             ;
//`ifdef alrera_ip
syncfifo_showahead_aclr_w320d32 measure_timestamps_buffer_inst(
    .data  ({iv_t4[95:16],iv_t3[95:16],iv_t2[95:16],iv_t1[95:16]}), 
    .wrreq (i_measure_state_wr),
    .rdreq (w_fifo_rden_ctx2fifo),
    .clock (i_clk),
    .aclr  (!i_rst_n), 
    .q     (wv_fifo_rdata_fifo2ctx),    
    .usedw (wv_fifo_data_count_fifo2ctx),
    .full  (), 
    .empty () 
);
//`endif
`ifdef xilinx_ip
syncfifo_showahead_aclr_w320d32 measure_timestamps_buffer_inst(
    .din        ({iv_t4[95:16],iv_t3[95:16],iv_t2[95:16],iv_t1[95:16]}), 
    .wr_en      (i_measure_state_wr),
    .rd_en      (w_fifo_rden_ctx2fifo),
    .clk        (i_clk),
    .srst        (!i_rst_n), 
    .dout       (wv_fifo_rdata_fifo2ctx),    
    .data_count (wv_fifo_data_count_fifo2ctx),
    .full       (), 
    .empty      () 
);
`endif

cpu_tx 
#(
.local_module_id(local_module_id)
)
cpu_tx_inst
(
    .i_clk                                 (i_clk                               ),
    .i_rst_n                               (i_rst_n                             ),
	                                        
	.iv_hcp_mid                            (iv_hcp_mid                          ),
	.iv_os_cid                             (iv_os_cid                           ),                                       
	.iv_port_ptp_enabled                   (iv_port_ptp_enabled                 ),    
    .iv_measure_sync_state_report_enabled  (iv_measure_sync_state_report_enabled),
    .i_cyclestart                          (i_cyclestart),	 
    
    .iv_frequency_cor                      (iv_frequency_cor  ),   
     
	.iv_gm_timestamps                      (iv_gm_timestamps         ),     
    .iv_correctfield_time                  (iv_correctfield_time     ),
    .iv_local_cnt_rx                       (iv_local_cnt_rx          ),
    .iv_sync_correctfield_time             (iv_sync_correctfield_time),
    .iv_sync_link_delay                    (iv_sync_link_delay       ),
    .i_time_info_valid                     (i_time_info_valid        ),
    
    .iv_clk_set                            (iv_clk_set            ),
    .i_clk_set_wr                          (i_clk_set_wr          ),
    .iv_current_local_count                (iv_current_local_count),
    .iv_current_sync_clk                   (iv_current_sync_clk   ),
    
    .i_sync_ok                             (i_sync_ok                           ),
	.iv_sync_abnormal_cnt                  (iv_sync_abnormal_cnt                ),
	.iv_offset                             (iv_offset                           ),
	.iv_csrateoffset_previousnode          (iv_csrateoffset_previousnode        ),
    .i_csrateoffset_previousnode_wr        (i_csrateoffset_previousnode_wr      ),
	.i_sync_state_wr                       (i_sync_state_wr                     ),
	                                        
	.iv_fifo_data_count                    (wv_fifo_data_count_fifo2ctx                  ),
    .o_fifo_rden                           (w_fifo_rden_ctx2fifo                         ),
    .iv_fifo_rdata                         (wv_fifo_rdata_fifo2ctx                       ),	
	                                        
	.ov_data                               (ov_data                             ),
	.o_data_wr                             (o_data_wr                           )
);

endmodule